Semiconductor chips are usually produced from large wafers of semiconductor material such as, for example, silicon or gallium arsenide, from which a plurality of chips can be produced The dimensions of the individual chips are delineated by scoring or grooving the wafer in checkerboard fashion. Each chip is provided with a circuit pattern by metallizing and etching through masks using standard photoresist methods. The final step of the process involves separating the individual chips from the wafer. If this is done by breaking or cutting along the grooves which delineate the boundaries of the individual chips, defects may result from cracked or chipped edges which are cosmetically unsightly and which may effect the performance of the chip.
Semiconductor chips can be produced having circuit patterns on both sides of the chip, or can be designed to connect to or interact with other electronic components or other semiconductor chips. Conductive via-holes are commonly used for connecting the circuit pattern for a chip on one side of the wafer to a corresponding circuit pattern on the other side of the chip, or for connecting the circuit on one side of the chip to a ground, to another electronic component, or to the circuit pattern on another chip.
Various techniques are known for providing conductive via-holes. In one such technique, metal pads are formed on the front side of the wafer, and holes are etched through the semiconductor chip from the back side of the wafer to abut the metal pads. This is followed by coating the inside of the hole and the back side of the wafer with a conductive metal layer using ordinary semiconductor processing techniques, such as sputtering or electroless plating. Finally, the structure is then electroplated using the metal pads and the conductive metal layer as a cathode to fill up the remainder of the via-hole.
Unfortunately, this method often leaves voids in the via-hole. During the electroplating, the higher electric field at the corners where the vertical walls of the holes intersect the horizontal surface of the wafer result in higher current densities and therefore higher plating rates. This causes the electroplated metal to be deposited more rapidly in the regions of higher electric field. As a result, the top of the hole adjacent to the back side of the wafer fills in more rapidly than the bottom of the hole abutting the metal pad. Eventually the top of the hole will close before the hole is completely filled, creating an unmetallized cavity inside the via hole. Further, undesirable surface irregularities, such as bumps, are formed on the back side of the wafer surrounding the holes due also to the higher electric field in these regions. These surface irregularities make it more difficult to form a secure structural bond to hold the chip in place. Finally, because the hole is created from the back of the wafer, time and effort and the use of infrared equipment is required to align the hole with the devices on the front side of the wafer.
In another technique proposed in U.S. Pat. No. 4,348,253 to Subbarao et. al., the holes used as vias are not terminated by metal pads. Circuit patterns are formed on the front side of the semiconductor wafer, holes are drilled through the wafer from the front side to the back using a precision laser, the wafer is metallized on the back side. The backside is then mounted on an electroplating block using an insulating adhesive layer, and the via is electroplated using the back side metallization as a cathode.
This approach is flawed in several ways. Because each hole in the wafer must be individually drilled using a precision laser, significant processing time is required. Further, local heating from the laser may cause surface and structural damage within the semiconductor material. Finally, this process may also produce voids in the via-hole adjacent to the adhesive layers.
Examples of other techniques of forming plated or metallized vias include the methods disclosed in U.S. Pat. No. 3,562,009 and U.S. Pat. No. 3,323,198 in which a laser beam and a high energy electron beam, respectively, are used to drill a hole through a wafer and a metal structure on the surface of the wafer, vaporizing the metal and depositing it on the inner surfaces of the hole. Once again, this involves significant processing time and may cause surface and structural damage within the semiconductor material.
Two improved methods for providing metallized vias are disclosed in our pending applications, Ser. No. 192,199 filed May 10, 1988 for a Method of Selective Via-Hole and Heat Sink Plating Using a Metal Mask filed May 10, 1988 and Ser. No. 192,343 filed May 10, 1988 for A Method of Forming Completely Metallized Via Holes in Semiconductors.
Plating on the edges of the chip would provide additional grounding and edge protection. None of the methods discussed above disclose a method for simultaneously forming plating on the edges of the chip while metallizing the via-holes.
Thus, the need exists for a simple method for providing plated vias from the front side of the wafer using a simple process flow which simultaneously forms wraparound plating.